1. Field of the Invention
The invention relates to a method for the internal monitoring of addressing circuits in semiconductor memories or data processing systems and to a semiconductor memory or a data processing system for carrying out the method.
2. Description of the Related Art
Error monitoring methods in semiconductor memories are known which can be used to recognize and possibly correct errors in data bits loaded in memory cells. These inherently known monitoring methods can recognize erroneous memory cell contents with a very high degree of coverage. This involves the use of error-recognizing and error-correcting codes such as ECC (Error Correction Codes), for example. For the protection of addressing circuits in semiconductor memories, these known methods cannot readily be used, however.
It is known that addressing circuits can be monitored by incorporating address bits into the calculation of redundant bits. However, this principle does not recognize addressing errors which were already present before the write address. By way of example, if a defective address decoder selects an incorrect word line, the word to be written is stored at an incorrect address. Upon subsequent read access using the same destination address, the word is read without the error which has occurred being recognized by means of the redundant bits calculated for the address.
In the method described in U.S. Pat. No. 6,754,858, error-recognizing and error-correcting codes are calculated and stored for the write addresses in synchronous dynamic RAM stores (SDRAM: Synchronous Dynamic Random Access Memory). To this end, a bit pattern is generated and also stored for a succession of write access operations. The value of this bit pattern is dependent on the individual write addresses and also on the order thereof. For the purpose of error recognition, a succession of read access operations is followed by comparison of a modeled bit pattern with the stored bit pattern. Errors which occur or are present in the addressing circuits usually prompt errors in a plurality of bits. The error recognition rate for multibit errors is too low for safety-critical applications, however.
In addition, the error recognition in line with U.S. Pat. No. 6,754,858 is based on the assumption that the addressing circuits are error-free during a write access operation. Particularly in the case of volatile memories, however, errors occur with not negligible frequency even in this case. In the case of nonvolatile memories, such as Flash ROMs, on the other hand, it is possible to check the memory in offline operation, which is unrewarding in the case of volatile memories.
In the self-test device for memories which is described in DE 43 17 175 A1, word lines are monitored by means of a current sensor. A current flowing through the sensor line is intended to indicate an error if a plurality of selection lines are activated simultaneously. However, the circuit arrangement described cannot recognize an internal error in the address decoder if a single, incorrectly addressed word line is selected. In addition, the method described deals merely with the monitoring of word lines downstream of the address decoder and address lines upstream of the address decoder. The address decoder may likewise produce errors, however, in which a single incorrect word line is selected despite correctly applied address lines. This type of error is not recognized using the method described, since the method is designed to recognize the selection of a plurality of word lines.
In addition, the precaution described provides a robust functionality only if each word line is connected to the sensor line only at a single point, however, for example when 2n test lines are being used for 2n word lines. However, when monitoring 2n word lines with n test lines, the problem of competing discharging and charging processes on the sensor line arises, the end result being dependent on many factors, such as on the address encoding of the word line under consideration, MOS process parameters and parasitic capacitances. If a word line is connected by a plurality of transistors on the sensor line, one transistor can discharge the sensor line on account of the error that is present while other transistors simultaneously charge the sensor line.
An incorrect word line selection can be recognized using the methods described in U.S. Pat. No. 4,912,710 and in the publication “Efficient UBIST Implementation for Microprocessor Sequential Parts”, M. Nicolaidis, IEEE International Test Conference, June 1990. In U.S. Pat. No. 4,912,710, an incorrect word line selection is recognized by comparing the actually selected address and the applied address. Nevertheless, the method presented in U.S. Pat. No. 4,912,710 cannot recognize a short circuit between selection lines, which involves the address bits of one selection line masking the other address bits. An example which may be mentioned in this context is a short circuit between the word lines which are selected using the address bits “111111 . . . 111” (all have the value one) and “110000 . . . 000”.
In the above publication by Nicolaidis, the actually selected address is identified using a simple code and not using the address bits which are to be expected. To ensure a high degree of coverage for the recognition of addressing errors, as few bit positions as possible in the codes have a logic value “1”. In the case of the cited example with what are known as “1-of-n codes”, each code comprises a single logic “1” value and a plurality of logic “0” values. Particularly in large memories, this method results in disadvantageously long codes, because the longer a code is the higher the hardware implementation costs of the method. By way of example, 1024 address test lines are required in order to monitor 10 address bits. Added to this also is the fact that testing the correspondence between the applied address and the recovered code becomes likewise more complex. For these reasons, the method described in the publication is also associated with a very high level of hardware implementation complexity.